Roadmap

What has shipped and what is under development.

v1 — Current Release

Feature	Status
Synthesizable SystemVerilog subset (IEEE 1800-2023)	Shipped
4-state simulation (0, 1, X, Z)	Shipped
Event-driven simulation kernel	Shipped
VPI / cocotb native integration	Shipped
Code coverage (line, branch, toggle) with LCOV output	Shipped
VCD / FST waveform generation	Shipped
IEEE 1735 IP encryption / decryption	Shipped
DPI interface	Shipped
Multi-distro Linux support (Ubuntu, Debian, Rocky, Fedora)	Shipped

v2 — Under Development In Progress

The v2 program is actively under development, targeting full IEEE 1800-2023 compliance. Features land incrementally as development progresses.

• Full IEEE 1800-2023 SystemVerilog Support
  • Behavioral constructs (delays, fork/join, process control)
  • Classes, randomization, and constraints
  • Native SystemVerilog testbenches (no longer VPI-only)
• Performance
  • Simulation engine optimizations
  • x86-64-v3 / v4 CPU architecture-level builds