What has shipped and what is planned.
v2.0 shipped. RyuSim v2 delivers full IEEE 1800-2023 testbench-language compliance; gate-level modeling (cl. 28–33) and the VPI assertion/coverage/data-read APIs (cl. 39–41) ship in v2.x. The per-clause status is in the compliance matrix; behavior that changed between v1 and v2 is enumerated in Migrating to v2.
Everything below is in the current release. The Since column marks what came with v1 and what v2.0 added.
| Capability | Since | Status |
|---|---|---|
| 4-state simulation (0, 1, X, Z) | v1 | Shipped |
| Synthesizable SystemVerilog (modules, generate, packages, interfaces, parameters) | v1 | Shipped |
| VPI / cocotb native integration | v1 | Shipped |
| Code coverage (line, branch, toggle) with LCOV output | v1 | Shipped |
| VCD / FST waveform generation | v1 | Shipped |
| IEEE 1735 IP encryption / decryption | v1 | Shipped |
| DPI interface | v1 | Shipped |
| Multi-distro Linux support (Ubuntu, Debian, Rocky, Fedora — supported versions) | v1 | Shipped |
| Stratified region scheduler (cl. 4) with suspendable processes | v2.0 | Shipped |
Behavioral timing — # delays (incl. intra-assignment), mid-procedure @, wait, timing in tasks (cl. 9, 10, 13) |
v2.0 | Shipped |
Native output — $display/$write/$monitor/$strobe and the $random family run in the design, not just over VPI (cl. 20, 21) |
v2.0 | Shipped |
fork/join/join_any/join_none, disable, wait fork, the process class (cl. 9) |
v2.0 | Shipped |
IPC — named event, semaphore, mailbox (cl. 15) |
v2.0 | Shipped |
| Dynamic data — queues, dynamic and associative arrays, array manipulation methods, string methods, packed multi-dimensional arrays (cl. 6, 7) | v2.0 | Shipped |
Classes and OOP — inheritance, virtual methods, $cast, parameterized and interface classes, virtual interfaces (cl. 8, 25) |
v2.0 | Shipped |
Randomization and constraints — rand/randc, constraint blocks, randomize() with, randcase/randsequence (cl. 18) |
v2.0 | Shipped |
| Functional coverage — covergroups, coverpoints, bins, crosses, coverage computation (cl. 19) | v2.0 | Shipped |
Clocking blocks, program blocks, final, $exit (cl. 14, 24) |
v2.0 | Shipped |
Assertions — immediate and concurrent SVA, sampled-value functions, sequence local variables, recursive properties, expect, let, assertion control (cl. 16) |
v2.0 | Shipped |
| Checkers (cl. 17) | v2.0 | Shipped |
DPI completion and the system-task long tail — UVM DPI helpers, file I/O, $dist_* (cl. 20, 21, 35) |
v2.0 | Shipped |
UVM — uvm_pkg compiles and runs; native SystemVerilog testbenches need no VPI |
v2.0 | Shipped |
| Design-true VCD / FST timescales (cl. 22) | v2.0 | Shipped |
Multi-core RTL evaluation (--threads), per-host -march detection, SIMD runtime dispatch |
v2.0 | Shipped |
These are the LRM areas RyuSim does not implement in v2.0. Gate-level modeling is the committed v2.1 theme — the first post-GA priority, not an open-ended backlog item.
| Area | Clause | Status |
|---|---|---|
| Gate-level and switch-level modeling, including strengths | 28 | v2.1 theme |
| User-defined primitives (UDPs) | 29 | v2.1 theme |
| Specify blocks | 30 | v2.1 theme |
| Timing checks | 31 | v2.1 theme |
| SDF back-annotation | 32 | v2.1 theme |
| Design configurations | 33 | Planned v2.x |
| VPI Assertion API | 39 | Planned v2.x |
| VPI Coverage Control API | 40 | Planned v2.x |
| VPI Data Read API | 41 | Planned v2.x |
--gpu flag still parses, prints a
deprecation warning, and has no effect (exit status is unchanged).v2 is the active line. The v1 maintenance branch is sunset as of the v2.0 release: v1 downloads stay hosted indefinitely, but no further v1 releases are planned. See Migrating to v2 for the sunset detail and the v1→v2 behavior deltas, and Downloads for installing a specific version or channel.