Features

What RyuSim simulates today, and what it does not yet.

Overview

SystemVerilog feature support

Category Feature Status
Process Blocks always_comb, always_ff, always_latch Supported
Process Blocks initial, final, always @() Supported
Process Blocks procedural delays (#) and event control Supported
Process Blocks fork/join, join_any, join_none, disable, wait fork Supported
Data Types logic, wire, reg, packed arrays, enums Supported
Data Types structs and unions, packed and unpacked Partial: tagged unions not yet (v2.x)
Data Types strings, event, variable lifetimes Supported
Data Types queues, dynamic arrays, associative arrays Supported
Data Types array methods and locators (clause 7.12) Supported
Data Types interconnect, trireg, user-defined nettypes Not yet (v2.x)
Classes classes, inheritance, virtual methods, $cast Supported
Classes parameterized and nested classes Supported
Randomization rand/randc, constraints, randomize() / with Supported
Randomization randcase, randsequence, $urandom family Supported
Functional Coverage covergroups, coverpoints, bins, crosses, options Partial: a covergroup declared inside a procedural block fails to compile
Assertions immediate and deferred assertions Supported
Assertions concurrent SVA: sequences, properties, local variables Supported
Assertions checkers (clause 17) Supported
Verification Blocks clocking blocks, program blocks Supported
Synchronization named events, semaphores, mailboxes Supported
Hierarchy module instantiation, generate for/if, packages Supported
Hierarchy interfaces, modports, virtual interfaces Supported
Operators arithmetic, logical, bitwise Supported
Operators shift (<<, >>, >>>, <<<) Supported
Operators concatenation, replication, ternary (?:) Supported
Operators assignment inside an expression, tagged-union expressions, streaming with a with clause Not yet (v2.x)
Control Flow if/else, case/casez/casex, loops Supported
Control Flow pattern matching (case … matches, if … matches) Not yet (v2.x)
Parameters parameter, localparam, parameter override Supported
Assignments continuous assign, blocking / non-blocking Partial: delays on continuous assignments and net declarations are ignored
Assignments intra-assignment timing controls Supported
Tasks & Functions tasks, functions, timing controls inside tasks Supported
System Tasks $display / $monitor family, severity tasks Supported
System Tasks file I/O, $dump*, `timescale handling Supported
Interop VPI (clauses 36–38) Partial: nine clause 38 routines missing
Interop DPI (clause 35) Partial: integral scalar arguments; see the DPI guide for the limits
Interop IEEE 1735 protected envelopes (clause 34) Supported
Gate Level gate primitives (clause 28) Partial: gate instances compute logic values; drive strengths and gate delays are ignored
Gate Level UDPs, specify blocks, timing checks, SDF, configurations (clauses 29–33) Not yet (v2.x)
Interop VPI assertion / coverage / data read APIs (clauses 39–41) Not yet (v2.x)

Some missing features, for example delays and drive strengths, compile without a diagnostic and have no effect. The matrix lists all of them under Accepted without a diagnostic.

This table summarizes the IEEE 1800-2023 compliance matrix, which gives the status and notes for every clause.