RyuSim v2 delivers full IEEE 1800-2023 testbench-language compliance; gate-level modeling (cl. 28–33) and the VPI assertion/coverage/data-read APIs (cl. 39–41) ship in v2.x.
Full 0, 1, X, Z value simulation with correct propagation semantics.
Design and testbench constructs alike: always_comb/ff/latch, generate, interfaces and packages, plus classes, dynamic types, fork/join, clocking and program blocks.
Write testbenches in SystemVerilog, or in Python with cocotb over the first-class VPI interface. Both are fully supported.
The full IEEE 1800-2023 clause 4 region scheduler — correct delta cycles, NBA ordering, and reactive-region semantics.
Immediate and concurrent SVA (clause 16) with sequences, properties and local variables, plus clause 17 checkers.
Clause 18 rand/randc, constraints and randomize() with a fixed seed-reproducibility contract, and clause 19 functional covergroups.
Line, branch, and toggle coverage with LCOV output. Coverage merge across test runs. Early
VCD and FST format output for waveform viewing in GTKWave or other viewers. Early
| Category | Feature | Status |
|---|---|---|
| Process Blocks | always_comb, always_ff, always_latch | ✅ Complete |
| Process Blocks | initial, final, always @() | ✅ Complete |
| Process Blocks | procedural delays (#) and event control |
✅ Complete |
| Process Blocks | fork/join, join_any, join_none, disable, wait fork | ✅ Complete |
| Data Types | logic, wire, reg, packed arrays, enums | ✅ Complete |
| Data Types | structs and unions (packed and unpacked; tagged unions in v2.x) | ✅ Complete |
| Data Types | strings, event, variable lifetimes |
✅ Complete |
| Data Types | queues, dynamic arrays, associative arrays | ✅ Complete |
| Data Types | array methods and locators (clause 7.12) | ✅ Complete |
| Classes | classes, inheritance, virtual methods, $cast |
✅ Complete |
| Classes | parameterized and nested classes | ✅ Complete |
| Randomization | rand/randc, constraints, randomize() / with |
✅ Complete |
| Randomization | randcase, randsequence, $urandom family |
✅ Complete |
| Functional Coverage | covergroups, coverpoints, bins, crosses, options | ✅ Complete |
| Assertions | immediate and deferred assertions | ✅ Complete |
| Assertions | concurrent SVA: sequences, properties, local variables | ✅ Complete |
| Assertions | checkers (clause 17) | ✅ Complete |
| Verification Blocks | clocking blocks, program blocks | ✅ Complete |
| Synchronization | named events, semaphores, mailboxes | ✅ Complete |
| Hierarchy | module instantiation, generate for/if, packages | ✅ Complete |
| Hierarchy | interfaces, modports, virtual interfaces | ✅ Complete |
| Operators | arithmetic, logical, bitwise | ✅ Complete |
| Operators | shift (<<, >>, >>>, <<<) | ✅ Complete |
| Operators | concatenation, replication, ternary (?:) | ✅ Complete |
| Control Flow | if/else, case/casez/casex, loops | ✅ Complete |
| Parameters | parameter, localparam, parameter override | ✅ Complete |
| Assignments | continuous assign, blocking / non-blocking | ✅ Complete |
| Assignments | intra-assignment timing controls | ✅ Complete |
| Tasks & Functions | tasks, functions, timing controls inside tasks | ✅ Complete |
| System Tasks | $display / $monitor family, severity tasks |
✅ Complete |
| System Tasks | file I/O, $dump*, `timescale handling |
✅ Complete |
| Interop | VPI (clauses 36–38), DPI (clause 35) | ✅ Complete |
| Interop | IEEE 1735 protected envelopes (clause 34) | ✅ Complete |
| Gate Level | gate primitives (clause 28) | ◑ Basic instances; completion in v2.x |
| Gate Level | UDPs, specify blocks, timing checks, SDF, configurations (clauses 29–33) | ✗ Ships in v2.x |
| Interop | VPI assertion / coverage / data read APIs (clauses 39–41) | ✗ Ships in v2.x |
This table is a summary. The authoritative, clause-by-clause status — including every partial and every post-GA item — is the IEEE 1800-2023 compliance matrix.
RyuSim v2 delivers full IEEE 1800-2023 testbench-language compliance; gate-level modeling (cl. 28–33) and the VPI assertion/coverage/data-read APIs (cl. 39–41) ship in v2.x.
Testbenches can be written natively in SystemVerilog or in Python with cocotb over the VPI interface — the v1 VPI contract is preserved. Every claim on this page maps to a clause in the compliance matrix.