Clause-by-clause status of the SystemVerilog standard in RyuSim v2.
RyuSim v2 runs the SystemVerilog testbench language natively, without VPI: classes, constrained randomization, covergroups, assertions, checkers, clocking and program blocks, process control and interprocess synchronization. Clauses 29–33 and 39–41 are not yet implemented and are scheduled for v2.x releases. Clauses 6, 7, 10, 11, 12, 19, 28, 35 and 36–38 and Annexes D and E are partial. The table below covers every clause of IEEE 1800-2023; each Partial row names what is missing. The rows were checked against RyuSim 2.1.16.
| Status | Meaning |
|---|---|
| Supported | The clause is implemented in the current release. |
| Partial | Part of the clause is implemented. The status cell names what is missing, and the notes say how RyuSim handles it. |
| Not yet (v2.x) | Not implemented in the current release. Scheduled for a v2.x release. |
Most missing constructs are rejected at compile time by the
unsupported-construct gate (--unsupported, default
error), with a message that starts
error: unsupported construct:. The exceptions are listed under
Accepted without a diagnostic.
| Clause | Topic | Status | Notes |
|---|---|---|---|
| 1–3 | Overview, references, building blocks | Supported | Slang-based frontend. |
| 4 | Scheduling semantics (stratified regions) | Supported | New in v2: the 17-region stratified event scheduler replaces the v1
settle loop. Since v2.1.11 the RTL part of a design runs as one
statically ordered pass per time slot, triggered by the signals that
changed. Combinational cycles are reported at compile time
(warning: combinational cycle through …) and run
as bounded loops, and always @* retriggers itself as
9.4.2.2 requires. Behavioral processes stay on the region queue. VPI
reads return current values. |
| 5 | Lexical conventions | Supported | Slang-based frontend. |
| 6 | Data types (nets, 4-state, strings, event, nettypes, lifetimes) |
Partial: interconnect, trireg, user-defined nettypes |
The three missing kinds are rejected at compile time and are
scheduled for v2.x. v1 covered nets, logic and strings;
the event type and variable lifetimes are new in
v2. |
| 7 | Aggregate types (arrays, queues, associative arrays, structs, unions) | Partial: tagged unions | Tagged unions are rejected at compile time and are scheduled for v2.x. New in v2: queues, dynamic arrays, associative arrays and the clause 7.12 array methods. v1 had unpacked arrays and flat structs only. |
| 8 | Classes | Supported | New in v2, including inheritance, parameterized and nested classes, and $cast. |
| 9 | Processes (always*/initial/final, fork/join, process control) |
Supported | v1 ran always* blocks to completion; the fork/join family, disable and std::process are new in v2. |
| 10 | Assignment statements (incl. intra-assignment timing) | Partial: delays on continuous assignments and net declarations | Intra-assignment timing controls are new in v2.
assign #5 y = a; and wire #5 y = a;
compile without a diagnostic, and y follows
a with no delay. force/release
on a net part-select works. |
| 11 | Operators and expressions | Partial: assignments in expression position (11.3.6), tagged-union expressions (11.9), streaming operators with a with clause (11.4.14.4) |
The three missing forms are rejected at compile time and are scheduled for v2.x. The rest of the operator and expression set shipped in v1 and moved onto the v2 typed IR. |
| 12 | Procedural statements | Partial: pattern matching (case … matches, if … matches, 12.6) |
Pattern matching is rejected at compile time and is scheduled for
v2.x. Procedural statements, loops,
case/casez/casex,
case … inside (12.5.4) and randcase
(new in v2) are supported. |
| 13 | Tasks and functions | Supported | Timing controls inside tasks are new in v2. |
| 14 | Clocking blocks | Supported | New in v2, including clause 14.14 global clocking. |
| 15 | Interprocess synchronization: semaphores, mailboxes, named events | Supported | New in v2. |
| 16 | Assertions (immediate + concurrent SVA) | Supported | New in v2. Assertions evaluate by default; --assertions=off disables them. |
| 17 | Checkers | Supported | New in v2. |
| 18 | Constrained random (rand, constraint, randomize) |
Supported | New in v2. An analytic layer and an embedded solver share the work, and the same seed gives the same stimulus. |
| 19 | Functional coverage (covergroups) | Partial: covergroup variables declared inside a procedural block | A covergroup handle declared at module scope works. Declared as a
local inside an initial block, it stops the compile
with an internal error (Error: typed codegen failed for
module …) instead of the unsupported-construct gate.
New in v2. This is separate from RyuSim's line, branch and toggle code coverage, which shipped in v1. |
| 20 | Utility system tasks and functions | Supported | Completed in v2. |
| 21 | I/O system tasks ($display family, file I/O, $dump*) |
Supported | v1 ran these only over the VPI path. v2 runs them in the design, file I/O included. |
| 22 | Compiler directives | Supported | `timescale is honored throughout, including the timescale written to waveform files. |
| 23 | Modules and hierarchy | Supported | Shipped in v1; moved onto the v2 typed IR. |
| 24 | Programs | Supported | New in v2, with Reactive-region scheduling and the implicit $finish. |
| 25 | Interfaces (incl. virtual interfaces) | Supported | Interfaces shipped in v1; virtual interfaces are new in v2. |
| 26 | Packages | Supported | Shipped in v1; moved onto the v2 typed IR. |
| 27 | Generate constructs | Supported | Shipped in v1; moved onto the v2 typed IR. |
| 28 | Gate-level and switch-level modeling | Partial: drive strengths, gate delays | Gate and switch primitives compute logic values (checked:
and, or, xor,
bufif1, nmos). Drive strengths and gate
delays compile without a diagnostic and have no effect: a
pull1 driver against a strong0 driver
resolves to x instead of 0, and
an and #5 gate changes its output with no delay.
buf (strong0, weak1) driving 1 reports
St1, not We1. Strengths and
switch-level modeling are scheduled for v2.x. |
| 29 | User-defined primitives (UDPs) | Not yet (v2.x) | Rejected at compile time
(error: unsupported construct: primitive). |
| 30 | Specify blocks | Not yet (v2.x) | Currently accepted and ignored without a diagnostic. Module path
delays such as (a => y) = 5 are not applied. |
| 31 | Timing checks | Not yet (v2.x) | Currently accepted and ignored without a diagnostic.
$setup and the other timing checks never report a
violation. |
| 32 | SDF back-annotation | Not yet (v2.x) | Accepted without a diagnostic. $sdf_annotate does
nothing. |
| 33 | Design configurations | Not yet (v2.x) | A config block in the sources is accepted and
ignored without a diagnostic. It cannot be named as the top level:
--top with a configuration's name fails with
Error: Top module '<name>' not found in design. |
| 34 | Protected envelopes (IEEE 1735) | Supported | Shipped in v1 and carried into v2. See the IP protection guide. |
| 35 | DPI (Direct Programming Interface) | Partial: scope functions, real arguments, packed-vector and aggregate arguments, c_identifier aliases, svGetTime* |
Imports, exports and the Annex-I svdpi.h header work
for integral scalar arguments; the UVM DPI helpers are new in v2.
Known limits: an import with no C definition returns 0 without a
diagnostic; svGetScope() and
svGetScopeFromName() return NULL;
real/shortreal arguments are mistyped;
packed vectors are passed by value instead of as
svBitVecVal*; unpacked-array, struct and output
string arguments fail in the C++ compiler rather than
at the unsupported-construct gate; an export in a module with two
instances runs in the last instance; the c_identifier
alias is ignored; svGetTime* and the deprecated svdpi
functions are missing. The DPI guide covers
each limit. |
| 36–38 | VPI overview, object model and routines | Partial: vpi_get64, vpi_get_data, vpi_put_data, vpi_get_delays, vpi_put_delays, vpi_get_value_array, vpi_put_value_array, vpi_handle_multi, vpi_handle_by_multi_index |
The simulation library does not provide the nine clause 38
routines listed. It provides the rest of clause 38, including
vpi_compare_objects, vpi_get_userdata and
vpi_put_userdata, which are new in v2. cocotb runs on
this set. |
| 39 | Assertion API | Not yet (v2.x) | This row is the VPI assertion API. The assertion language (clauses 16–17) is supported. |
| 40 | Coverage control API | Not yet (v2.x) | This row is the VPI coverage control API. Covergroups in the language are clause 19; see that row for their status. |
| 41 | Data read API | Not yet (v2.x) | |
| Annex D/E | Optional system tasks and compiler directives | Partial: most Annex D system tasks | $countdrivers runs. $getpattern,
$input, $key/$nokey,
$list, $log/$nolog,
$reset, $save/$incsave/$restart,
$scope, $showscopes,
$showvars and $sreadmemh are rejected at
compile time. The Annex E directives
(`default_decay_time,
`default_trireg_strength,
`delay_mode_*) are accepted without a diagnostic. |
These constructs compile with no error or warning, even with the default
--unsupported=error, and do not have their IEEE 1800-2023
effect. A design whose results depend on them simulates incorrectly without
telling you:
assign #5, wire #5) and on gate instances
(clauses 10 and 28).$sdf_annotate (clause 32).config blocks (clause 33).This is the complete list of what is not yet implemented:
interconnect and trireg (clause 6); tagged unions (7, 11); continuous-assignment and net delays (10); the clause 11 and 12 forms named in their rows; covergroups declared in procedural blocks (19); the DPI limits (35)This matrix describes the current release. The roadmap gives the order of upcoming work and the features page gives an overview.