Clause-by-clause status of the SystemVerilog standard in RyuSim v2.
RyuSim v2 delivers full IEEE 1800-2023 testbench-language compliance; gate-level modeling (cl. 28–33) and the VPI assertion/coverage/data-read APIs (cl. 39–41) ship in v2.x. This page is the per-clause detail behind that statement — every clause of the standard, with its status in the shipped v2 release.
| Status | Meaning |
|---|---|
| ✅ Complete | The clause is implemented in the shipped v2 release. |
| ◑ Partial | A documented subset is implemented; the remainder is scheduled. The scope of what works is stated in the notes. |
| ✗ v2.x | Not implemented in v2.0/v2.0.1 — scheduled for a v2.x release. |
| Clause | Topic | Status | Notes |
|---|---|---|---|
| 1–3 | Overview, references, building blocks | ✅ Complete | Slang-based frontend. |
| 4 | Scheduling semantics (stratified regions) | ✅ Complete | New in v2: the full 17-region stratified event scheduler, replacing v1's settle-loop approximation. |
| 5 | Lexical conventions | ✅ Complete | Slang-based frontend. |
| 6 | Data types (nets, 4-state, strings, event, nettypes, lifetimes) |
✅ Complete | v1 covered nets, logic and strings; the event type and
variable lifetimes are new in v2. interconnect, trireg and
user-defined nettypes are diagnosed at compile time and ship in v2.x. |
| 7 | Aggregate types (arrays, queues, associative arrays, structs, unions) | ✅ Complete | New in v2: queues, dynamic arrays, associative arrays and the cl. 7.12 array methods. v1 had unpacked arrays and flat structs only. Tagged unions are diagnosed at compile time and ship in v2.x. |
| 8 | Classes | ✅ Complete | New in v2, including inheritance, parameterized and nested classes, and $cast. |
| 9 | Processes (always*/initial/final, fork/join, process control) |
✅ Complete | v1 ran always* blocks to completion; the fork/join family, disable and std::process are new in v2. |
| 10 | Assignment statements (incl. intra-assignment timing) | ✅ Complete | Intra-assignment timing controls are new in v2. Delays on continuous assignments,
and force/release on part-selects, have known residuals. |
| 11 | Operators and expressions | ◑ Partial | The operator and expression set shipped in v1 and is migrated onto the v2 typed
IR. Assignments in expression position (11.3.6), tagged-union expressions (11.9)
and streaming operators with a with clause (11.4.14.4) are diagnosed
at compile time and ship in v2.x. |
| 12 | Procedural statements | ◑ Partial | Procedural statements, loops, case/casez/casex
and randcase (new in v2) are supported. Pattern matching
(case … matches, if … matches, 12.6) and
case … inside (12.5.4) are diagnosed at compile time and ship
in v2.x. |
| 13 | Tasks and functions | ✅ Complete | Timing controls inside tasks are new in v2. |
| 14 | Clocking blocks | ✅ Complete | New in v2, including cl. 14.14 global clocking. |
| 15 | Interprocess synchronization: semaphores, mailboxes, named events | ✅ Complete | New in v2. |
| 16 | Assertions (immediate + concurrent SVA) | ✅ Complete | New in v2. Assertions evaluate by default; --assertions=off disables them. |
| 17 | Checkers | ✅ Complete | New in v2. |
| 18 | Constrained random (rand, constraint, randomize) |
✅ Complete | New in v2, on a hybrid analytic + embedded-solver engine with a fixed seed-reproducibility contract. |
| 19 | Functional coverage (covergroups) | ✅ Complete | New in v2 — distinct from RyuSim's line/branch/toggle code coverage, which shipped in v1. |
| 20 | Utility system tasks and functions | ✅ Complete | Completed in v2. |
| 21 | I/O system tasks ($display family, file I/O, $dump*) |
✅ Complete | v1 served these only over the VPI path; v2 implements them natively, including file I/O. |
| 22 | Compiler directives | ✅ Complete | Design-true `timescale handling end-to-end, including waveform time units. |
| 23 | Modules and hierarchy | ✅ Complete | Shipped in v1; migrated onto the v2 typed IR. |
| 24 | Programs | ✅ Complete | New in v2, with Reactive-region scheduling and implicit $finish. |
| 25 | Interfaces (incl. virtual interfaces) | ✅ Complete | v1 had strong interface support; virtual interfaces are new in v2. |
| 26 | Packages | ✅ Complete | Shipped in v1; migrated onto the v2 typed IR. |
| 27 | Generate constructs | ✅ Complete | Shipped in v1; migrated onto the v2 typed IR. |
| 28 | Gate-level and switch-level modeling | ◑ Partial | Basic gate instances work. Strengths and switch-level modeling ship in v2.x. |
| 29 | User-defined primitives (UDPs) | ✗ v2.x | Scheduled post-GA. |
| 30 | Specify blocks | ✗ v2.x | Scheduled post-GA. |
| 31 | Timing checks | ✗ v2.x | Scheduled post-GA. |
| 32 | SDF back-annotation | ✗ v2.x | Scheduled post-GA. |
| 33 | Design configurations | ✗ v2.x | Scheduled post-GA. |
| 34 | Protected envelopes (IEEE 1735) | ✅ Complete | Shipped in v1 and carried through v2 — see the IP protection guide. |
| 35 | DPI (Direct Programming Interface) | ✅ Complete | v1 shipped the scope API, marshaling and imports; the Annex-I svdpi.h surface and the UVM DPI helpers are new in v2. |
| 36–38 | VPI overview, object model and routines | ✅ Complete | v1's VPI surface was already strong; v2 completes the cl. 38 routines (put_data/get_data, delays, compare_objects, userdata) and the remaining callbacks. |
| 39 | Assertion API | ✗ v2.x | Scheduled post-GA. The assertion language (cl. 16–17) is complete; this row is the VPI control API. |
| 40 | Coverage control API | ✗ v2.x | Scheduled post-GA. Covergroups themselves (cl. 19) are complete. |
| 41 | Data read API | ✗ v2.x | Scheduled post-GA. |
| Annex D/E | Optional system tasks and compiler directives | ◑ Partial | The commonly-used set is implemented; the long tail continues in v2.x. |
Everything not complete in v2 is a single, named list — there is no undocumented remainder:
This matrix tracks the shipped release. See the roadmap for sequencing and the features page for the capability overview.