Install RyuSim and run a first design, then use the guides for each task and the reference pages for every option and IEEE 1800 clause.
Install RyuSim, compile and run a design, and run a cocotb test.
Run cocotb testbenches through the Makefile flow, the Python Runner, the pytest plugin or cocotb-test.
Collect line, branch, toggle, assertion and covergroup coverage, and merge runs into one LCOV file.
Write VCD and FST waveforms and open them in GTKWave or Surfer.
Call C from SystemVerilog and SystemVerilog from C.
Threads, optimization levels, 2-state mode and how to measure a run.
X-initialization, zero-initialization and 2-state mode, and why results differ.
Simulate encrypted SystemVerilog IP with broker-based key management.
Every option of ryusim, ryusim compile, ryusim coverage and ryusim profile.
Status of each IEEE 1800-2023 clause in RyuSim v2.
Error messages you may see, what causes them and how to fix them.