v2.1.18 Release

A SystemVerilog simulator

RyuSim compiles SystemVerilog designs and testbenches to C++ and runs them as a 4-state, event-driven simulation on Linux. Testbenches are written in SystemVerilog or in Python with cocotb. Free to use; not open source.

Get Started View Features

curl -fsSL https://ryusim.com/install.sh | bash

Linux only. Windows users: use WSL2.

What RyuSim does

Simulates 0, 1, X and Z on the IEEE 1800-2023 stratified event scheduler.
Runs SystemVerilog testbenches without VPI: classes, randomization, covergroups, SVA, fork/join.
Runs Python testbenches with cocotb, which drives the design through VPI.
Collects line, branch and toggle coverage into an LCOV file, alongside covergroups.
Writes VCD and FST waveforms.

Not yet supported: drive strengths, gate and continuous-assignment delays, switch-level strengths, UDPs, specify blocks, timing checks, SDF and design configurations (clauses 28–33), and the VPI assertion, coverage and data-read APIs (clauses 39–41). Some of these compile without a diagnostic and have no effect; the compliance matrix lists which, with the status of every clause; planned work is on the roadmap.