v2.0.10 Release

SystemVerilog Simulation,
Simplified.

A high-performance 4-state simulator for SystemVerilog designs and testbenches, with native cocotb/VPI integration. Free for everyone.

Get Started View Features
curl -fsSL https://ryusim.com/install.sh | bash

Linux only. Windows users: use WSL2.

Feature Highlights

4-State Simulation

Full X/Z propagation on an IEEE 1800-2023 clause 4 stratified event kernel.

Native SV & cocotb Testbenches

Write testbenches natively in SystemVerilog — classes, randomization, covergroups, SVA — or in Python with cocotb over the first-class VPI interface.

Coverage, Built In

Line, branch, and toggle code coverage with LCOV output, plus clause 19 functional covergroups.

RyuSim v2 delivers full IEEE 1800-2023 testbench-language compliance; gate-level modeling (cl. 28–33) and the VPI assertion/coverage/data-read APIs (cl. 39–41) ship in v2.x. — see the per-clause matrix.